Computers have long been utilized to assist engineers in the design of electronic circuits, in particular to assist in the design of integrated circuits. Computer aided engineering (hereinafter CAE) design tools assist the user in the initial design of functional circuitry through the use of a graphical user interface. In general, such CAE design tools permit a user to select an electronic component useful for the intended application from a menu of components known to the system. Next, the tools typically permit a user to place a graphical representation of the selected component on the graphic display screen. Appropriate graphical connections, representing electrical interconnections, between the newly placed component and previously placed components are then "drawn" by the user through the graphical user interface. Tools such as described above which interact with a user to create a graphical representation of the intended application circuit are often referred to as design capture tools.
Following design capture, many other types of CAE tools are known to assist a design engineer in other aspects of the application circuit design. CAE tools are known to perform simulation of the circuits to help locate functional errors in the design. Other tools are used to perform physical layout of the circuit either in the form of discrete components on a printed circuit board, or in the form of custom circuits within an integrated circuit package (known as application specific integrated circuits and hereinafter referred to as ASIC).
ASICs may be designed and implemented using a variety of different chip design products and methods. These methods include "full custom" chip design in which a designer plans the layout and interconnection of every component down to the lowest levels such as individual transistors, capacitors, resistors and the like. Full custom chip design permits the designer to carefully plan every aspect of the chip design to optimize for performance, power management, and physical size. Though full custom chip design allows for the maximum flexibility in design choices, there is usually a significant cost due to complexity of the design and manufacturing processes.
The complexity of full custom chip design is somewhat reduced by use of "gate arrays" in ASIC design. Gate arrays are ASICs in which the designer uses standard components having a higher level of integration to implement the ASIC rather than using exclusively individual transistors and other low level components. In gate array ASIC designs, a designer constructs the desired application circuit utilizing higher level components such as logic gates. A designer may more rapidly design and implement an ASIC using these higher level components but some flexibility may be sacrificed in areas such as performance. "Standard cell" design tools and methods provide component libraries with still higher levels of integration to thereby further simplify the design process. In standard cell design processes, a designer selects among standard functional cells such as adders, decoders, flip-flops, latches, multiplexors, etc. The use of these standard cells which have a higher level of integration further enhances the speed with which a designer may implement an ASIC.
The process of "laying out" an ASIC involves determining a physical placement of the desired circuit components within the integrated circuit (hereinafter IC) package design in such a way as to optimize for parameters such as performance, physical space, and power dissipation. The layout tasks include placement of the desired components as well as routing of interconnection conductor signal paths between the components. In full custom ASIC designs, the designer may interact with CAE tools to control the placement and routing of each low level component in the ASIC. Placing related components closer to one another may improve performance, for example, by reducing the capacitive loads due to length of the interconnection leads between signals to thereby reduce the propagation delays between components. The layout process involves tradeoffs in several interrelated aspects of the ASIC design. Often, a placement of a component in one location within the ASIC will improve the circuit's performance with respect to one parameter but degrade the performance with respect to another parameter. Or a particular placement may improve performance relative to one interconnect path but degrade performance for another path. In gate array or standard cell ASIC designs, other physical constraints of the ASIC layout are imposed by the physical construction of the components within the manufactured IC package. CAE tools typically automate the placement and layout of the components within the gate array or standard cell IC package while attempting to satisfy, primarily, surface area design constraint specifications.
Balancing these tradeoffs can require changing, or swapping, a component selected by the designer to a functionally equivalent component optimized for a different performance, area, or power dissipation goal. Clearly, it is known in the art for a designer to perform such swapping of components manually by iteratively re-designing and analyzing the ASIC. Determining the appropriate balance of these tradeoffs requires analysis of the ASIC design. To analyze an ASIC design with respect to timing, a designer first specifies timing constraints for input or output connections to pins on the IC package for connecting the ASIC chip to other devices. Next, the designer uses CAE analysis tools to determine if the design meets the specified constraints.
Static timing analysis CAE tools are used to automate computation of timing performance of signals within the ASIC design. An ASIC designer, aided by CAE tools, compares the timing estimates produced by such static timing analysis tools to the design constraints to determine whether all constraints have been met. Simulation CAE tools are also common to simulate the actual operation of the ASIC design against a set of test input vectors to determine whether the ASIC design violates any functionality or timing constraints when simulating operation on actual test data inputs. Prior CAE tools, often in conjunction with the designer's manual intervention, iteratively attempted many component placement options to correct any violations of the specified constraints. In the event no satisfactory placement could be determined, CAE design tools informed the user to permit correction of the violation by re-design of the ASIC. A designer could then correct the violation by selecting an alternate component with different operating characteristics.
In standard cell design methodologies, as well as other methods, it is common for a CAE design tool to provide a library of available components which include a variety of functionally equivalent components each having different operating characteristics (such as variable timing specifications or drive power etc.). It is a time consuming process for a designer to manually review the simulation or static timing analysis results and redesign the ASIC to swap components in hopes of eliminating the design constraint violations. In addition, the process could be iterative in that a possible component swap selection may improve design margins with respect to constraints for some interconnect paths while degrading margins in other interconnect paths. The designer must typically verify timing constraints to evaluate the efficacy of the possible component selected for the swap. Several re-design, re-simulate iterations may be required to find an appropriate alternate component selection to resolve any constraint violations.
Methods common to prior CAE design tools attempt to assist the designer in automating the placement, layout and routing of gate array and standard cell ASIC designs. One prior approach, typified by the Synopsys In Place Optimization (IPO) produced by Synopsis, Inc. in their Design Compiler product, is to require an ASIC designer to identify all interconnection paths for which timing constraints are critical and a set of components which may be substituted to attempt to improve the interconnection path timing. The Synopsys IPO method evaluates timing for all critical paths identified by the designer to locate timing violations in the ASIC design and to identify possible component swaps to improve the timing. This method, however, depends upon the manual intervention of the designer to specify correctly and completely required timing constraints needed to identify the critical paths to be checked and the functionally equivalent components available for possible component swaps. In addition, the IPO method does not evaluate interconnection paths other than the critical paths and therefore may not fully optimize the entire ASIC design and layout. This excludes, for example, delay paths for asynchronous circuits which are difficult to analyze with static timing analysis tools.
Other prior designs have attempted to further automate the layout phase of an ASIC design to determine appropriate tradeoffs in the circuit layout versus the design constraint parameters specified by the designer. In U.S. Pat. No. 5,218,551, issued Jun. 8, 1993, Agrawal et al. disclose a timing driven placement method which attempts to move portions of the circuit design between areas ("precincts") of the ASIC to minimize propagation delays. The placement method disclosed by Agrawal does not address the delays imposed by physical routing constraints of the interconnection conductor signal paths. Agrawal's method only considers estimates of the capacitive loads and delays associated with the interconnection of the placed components. Such timing estimates are derived by operation of static timing analysis CAE tools. Until the ASIC design is placed and all interconnections are routed, precise delay estimates are unavailable. In addition, Agrawal's reliance on static timing analysis renders the method less useful to ASIC designs which include asynchronous functional components. Static timing analysis tools require a designer to supply all timing relationship constraints to properly analyze the operation of the circuit. Designers of asynchronous ASIC designs cannot always fully specify the timing constraints required for static timing analysis. Agrawal's method leaves as a task for other tools and methods to resolve "timing and wiring" problems.
U.S. Pat. No. 5,173,864, issued Dec. 22, 1992 to Watanabe et al., discloses a standard cell component which provides a programmable delay time between its input signal and its corresponding output signal. This variable delay standard cell component may be used by a designer in the interconnection between other standard cell components. CAE tools may then automatically adjust the timing of the variable delay standard cell to alter propagation delays along a signal interconnection path. Watanabe's variable delay standard cell allows the timing to be adjusted without replacing other standard cell components in the ASIC design. However, this method and apparatus only permit the addition of delays to signal interconnection paths. This method and apparatus does not address the design issues surrounding reduction of the interconnection propagation delays. In addition, the methods disclosed by Watanabe are not assured to terminate (converge) with an improved design to satisfy the required timing constraints of the ASIC design. Watanabe makes only vague reference to a determination that a particular change to the delay on one isolated interconnection signal path is "OK." There is no disclosure with regard to what measures are used to make that determination, nor to the possibility that a change may be "OK" with respect to one interconnection signal path but may unacceptably degrade another interconnection signal path.
Dunlop et al., in U.S. Pat. No. 4,827,428, issued May 2, 1989, discusses a method for altering the size of individual transistors in a full custom ASIC design to meet user defined timing constraints on user identified critical paths. As discussed above with respect to Agrawal, Dunlop's method uses only timing estimates derived from static timing analysis CAE tools for identified critical paths. These estimates fail to take into account more precise determination of the interconnection signal propagation delay times available after routing of the ASIC interconnections.
In U.S. Pat. No. 4,698,760, issued Oct. 6, 1987 to Lembach et al., a method is disclosed to optimize signal timing and power dissipation in IC designs. Like other prior designs discussed above, Lembach's method is used at the design phase before completion of layout placement and routing. Because of this limitation, Lembach's method relies on inaccurate estimates of interconnection propagation delays.
In addition to the above problems, Dunlop's and Lembach's methods, like Watanabe's method, are iterative in such a manner that they are neither assured to complete nor to converge on improved timing. Under certain pathological design constraints, all three methods may loop infinitely never converging on improved designs for the ASIC timing constraints.
Finally, in addition to the above identified problems, Lembach's and Watanabe's methods, like Agrawal's method, rely on static timing analysis to estimate the actual timing of the selected components and associated interconnection signal paths. As discussed above, reliance on static timing analysis renders all three methods less useful to ASIC designs which include asynchronous functional components. Static timing analysis tools must be supplied with all timing relationship constraints to properly operate. Designers of asynchronous ASIC designs cannot always fully specify the timing constraints required for static timing analysis. Extensive timing constraints may be needed from the designer in order to fully analyze the ASIC design with static timing analysis tools. Another problem arises in the tendency of static timing analysis tools generating erroneous or false paths: paths identified as critical which are not valid.
It is therefore apparent that a need exists in CAE ASIC design tools for an improved method to automatically select an optimum, functionally equivalent circuit component for swapping with a circuit component selected by the designer in an ASIC layout when the designer's component selection violates design constraints such as signal timing.